AI Insights
NVIDIA

Senior I/O Subsystem Architect

NVIDIA · Santa Clara, California, US
full-timestaff (10-20 yrs)Posted 22d ago
Hardware EngineeringIC4IC + ManagementHybrid
StackNVLinkPCIeUCIeCXLCHIAXIChip-to-Chip InterconnectsLink Layer ArchitectureTransaction LayerData Link LayerPhysical LayerSoC ArchitectureArchitectural ModelingFirmwareSystemCHardware Description LanguagesIP IntegrationPackage DesignVerificationProtocol Design

Summary

Senior I/O Architect role on NVIDIA's NVLink chip-to-chip team, responsible for defining next-generation chip interconnect standards and products across the full product lifecycle — from requirements through deployment — at one of the most prestigious semiconductor companies in the world.

About the role

We are now looking for a Senior I/O Architect for our NVLink chip to chip team!

NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols. You’ll be part of a team responsible for defining next generation communications standards and products building on our current NVLink technology. The job scope ranges from developing initial product requirements, working with research, other architects, software/firmware and product development teams to shepherd the design through all phases of the product lifecycle.
 

What you will be doing:

  • Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency

  • Working with other design teams to define interfaces and flows between NVLink C2C blocks and the rest of the chip

  • Architectural modeling, validation, definition and documentation

  • Driving implementation across design, verification, firmware and software teams

  • Working with various teams to define NVLink C2C architecture
     

What we need to see:

  • MS or PhD in Electrical Engineering, Computer Science or Computer Engineering (or equivalent experience)

  • 10+ years of relevant experience in some combination of architecture, design, and verification

  • Proven experience over link layer architecture (Transaction layer, Data link layer, Physical layer)

  • Experience with existing interconnects (PCIE, UCIE, Chip to Chip links) and knowledge of Industry standard protocols CHI/CXL/AXI

  • Able to define system architecture with NVLINK-C2C interconnects and SW stack around it

  • Collaborate with multi-functional teams including IP, SoC, physical/package design, firmware, electrical design, and validation to drive interconnect technology development and integration

  • Evaluate and trade off technical solutions to meet platform requirements for current and future products

  • Have completed and shipped multiple projects and are skilled at I/O Architecture
    Experience leading projects from concept through product lifecycle, including pathfinding, prototyping, and deployment
     

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you!
 

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 224,000 USD - 356,500 USD for Level 5, and 272,000 USD - 431,250 USD for Level 6.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until March 13, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

What you'll do

1Research and craft architecture solutions for chip-to-chip communication optimizing for performance, area, power, security, and resiliency
2Work with design teams to define interfaces and flows between NVLink C2C blocks and the rest of the chip
3Perform architectural modeling, validation, definition, and documentation
4Drive implementation across design, verification, firmware, and software teams
5Collaborate with multi-functional teams including IP, SoC, physical/package design, firmware, electrical design, and validation
6Evaluate and trade off technical solutions to meet platform requirements for current and future products
7Develop initial product requirements and shepherd design through all phases of the product lifecycle
8Work with research teams to develop next-generation NVLink technology

Requirements

10+ years of experience in a combination of chip architecture, design, and verification with demonstrated shipped products
Deep expertise in link layer architecture spanning Transaction, Data Link, and Physical layers
Hands-on experience with industry-standard interconnect protocols including PCIe, UCIe, CXL, CHI, and AXI
Ability to define end-to-end system architecture integrating NVLink C2C interconnects with the surrounding software stack
Proven track record leading cross-functional projects from concept through full product lifecycle including pathfinding, prototyping, and deployment

Nice to have

CXL
UCIe
SystemC modeling
PHY design experience
Software stack definition
Power/area/performance trade-off analysis
Pathfinding and prototyping

Role overview

Role family
Hardware Engineering
Level
IC4 — other
Experience
10–20 years
Type
Hybrid (IC + Management)
Remote policy
Hybrid
Visa sponsorship
Not offered

Tech stack analysis

TOOLS
Architectural modeling toolsVerification environments

Green flags

7 items
Salary range fully disclosed with two level bands ($224K–$431K base), rare transparency for semiconductor industry postingscompensation

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Benefits breakdown

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Hiring insights

JD quality
8/10
Urgency
medium
Autonomy
high
Team size
medium (5-15)

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Red flags

PRO3 items
Extremely broad and demanding requirements (MS/PhD + 10+ years + multiple shipped products + cross-disciplinary expertise) may indicate a very narrow candidate pool or elevated barrequirements

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Interview insights

PRO
Rounds
5
Duration
6 wks
Difficulty
very hard
Take-home
No

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Career path

PRO
Next roles
Principal I/O ArchitectDistinguished Engineer – InterconnectsSenior Director of Architecture

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About the company

NVIDIA is the world's leading designer of GPUs and AI computing platforms. Its chips power everything from gaming and data centers to autonomous vehicles and scientific research. With a market cap exceeding $2 trillion, NVIDIA's CUDA platform and AI accelerators have become the backbone of the global AI revolution.

HQSanta Clara, CA, USA
Interview difficultyvery hard
Build vs Maintainbuild
Cross-functionalYes