AI Insights
NVIDIA

Principal DRAM Architect – GPU Memory Solutions

NVIDIA · Santa Clara, California, US
full-timestaff (15-30 yrs)Posted 30d ago
Hardware EngineeringIC5IC + ManagementHybrid
StackHBM (HBM2/2e/3/3e)GDDR6/7LPDDR5/6DRAM ArchitectureTSV DesignDie StackingCoWoS IntegrationInterposer DesignFOWLPECC/CRCRefresh Scheme DesignPHY DesignSI/PI AnalysisTiming Margin AnalysisEqualizationJitter BudgetingAdvanced PackagingHybrid BondingJEDEC StandardsPower ManagementThermal Management3D DRAMMRAMRRAMEUV Process TechnologyHPC Architecture

Summary

NVIDIA is hiring a Principal DRAM Architect to define and drive next-generation AI and graphics memory architecture, roadmap, and implementation — spanning HBM, GDDR, and LPDDR technologies across AI accelerators, data center, graphics, and automotive platforms.

About the role

NVIDIA is seeking a world-class Principal DRAM Architect to define, drive, and deliver the architecture, roadmap, and implementation of next-generation AI and graphics memory solutions! This role sits at the intersection of I/O design, advanced packaging, and process technology, with a mission to co-optimize DRAM, GPU, and system architectures to achieve unprecedented performance, efficiency, and reliability.
 

As part of NVIDIA’s Memory Architecture team, you will shape the evolution of cutting-edge memory technologies — from TSV stacking and refresh management to advanced reliability and retention schemes — while collaborating closely with leading DRAM vendors and JEDEC working groups to influence global memory standards! Familiarity with HBM, GDDR, and LPDDR is highly valued, enabling broad architectural impact across NVIDIA’s full product portfolio spanning AI accelerators, graphics, data center, and automotive platforms.


What You’ll Be Doing:

  • Architect next-generation DRAM solutions and NVIDIA-specific implementations — including bank and stack structures, refresh mechanisms, retention schemes, ECC/CRC, power management, and reliability optimization.

  • Lead innovation in high-speed memory interfaces, with deep expertise in HBM PHYs (wide I/O, TSV signaling, SI/PI, timing margins) and an understanding of GDDR/LPDDR PHY architectures.

  • Collaborate across domains on advanced packaging technologies (TSVs, interposers, CoWoS, hybrid bonding, FOWLP) to optimize DRAM–GPU co-packaging for bandwidth, power, thermal performance, and yield.

  • Evaluate emerging DRAM process nodes (sub-1x nm, EUV, new capacitor/dielectric materials) and their impact on density, power, retention, and cost.

  • Influence industry direction by working with DRAM vendors and actively contributing to JEDEC committees, driving next-generation memory standards and NVIDIA-specific roadmap alignment.

  • Model and quantify system-level trade-offs in bandwidth, latency, power, cost, yield, and thermal behavior to guide architectural decisions.

  • Mentor engineers, lead technical reviews, and shape NVIDIA’s long-term memory architecture vision.
     

What We Need to See:

  • MS or PhD in Electrical Engineering, Computer Engineering, Physics (or equivalent experience).

  • 15+ years of experience in DRAM or memory system architecture, with at least 5+ years focused on HBM (HBM2/2e/3/3e or next-gen).

  • Expertise in HBM architecture: TSV design, die stacking, interposer/CoWoS integration, refresh schemes, ECC/CRC, pseudo-channels, and thermal/power management.

  • Proven participation in JEDEC or equivalent standards organizations, contributing to DRAM or HBM specifications.

  • Demonstrated ability to influence DRAM vendor roadmaps, negotiate trade-offs, and enable early silicon validation.

  • Strong understanding of I/O and PHY design fundamentals — timing, SI/PI, equalization, jitter budgeting.

  • Proven experience balancing system-level trade-offs across performance, bandwidth, power, cost, yield, and reliability.

  • Exceptional technical leadership and cross-functional communication skills.
     

Ways to Stand Out from the Crowd:

  • Hands-on experience with GDDR6/7 and LPDDR5/6 architectures — including bank management, signaling, power states, and error handling.

  • Deep understanding of thermal and mechanical challenges in advanced memory packaging and 3D integration.

  • Familiarity with emerging memory technologies (3D DRAM, MRAM, RRAM, or next-gen hybrid memory).

  • Publications, patents, or JEDEC leadership roles demonstrating influence on memory architecture and standards.

  • Background in high-bandwidth computing platforms — AI, HPC, or graphics accelerators.
     

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant people in the world working for us and, due to unprecedented growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 272,000 USD - 431,250 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until February 24, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

What you'll do

1Architect next-generation DRAM solutions including bank/stack structures, refresh mechanisms, retention schemes, ECC/CRC, power management, and reliability optimization
2Lead innovation in high-speed memory interfaces with deep HBM PHY expertise (TSV signaling, SI/PI, timing margins) and understanding of GDDR/LPDDR PHY architectures
3Collaborate on advanced packaging technologies (TSVs, interposers, CoWoS, hybrid bonding, FOWLP) to optimize DRAM–GPU co-packaging for bandwidth, power, thermal, and yield
4Evaluate emerging DRAM process nodes (sub-1x nm, EUV, new capacitor/dielectric materials) and their impact on density, power, retention, and cost
5Influence industry direction by collaborating with DRAM vendors and contributing to JEDEC committees to drive next-generation memory standards
6Model and quantify system-level trade-offs in bandwidth, latency, power, cost, yield, and thermal behavior
7Mentor engineers, lead technical reviews, and shape NVIDIA's long-term memory architecture vision

Requirements

15+ years of DRAM or memory system architecture experience, with 5+ years focused specifically on HBM (HBM2/2e/3/3e or next-gen)
Deep expertise in HBM architecture including TSV design, die stacking, interposer/CoWoS integration, refresh schemes, ECC/CRC, pseudo-channels, and thermal/power management
Proven participation and contribution to JEDEC or equivalent standards organizations for DRAM/HBM specifications
Strong understanding of I/O and PHY design fundamentals — timing, SI/PI, equalization, and jitter budgeting
Demonstrated ability to influence DRAM vendor roadmaps, balance system-level trade-offs, and enable early silicon validation

Nice to have

GDDR6/7
LPDDR5/6
3D DRAM
MRAM
RRAM
Thermal and mechanical packaging analysis
Publications or patents in memory architecture
JEDEC leadership roles
AI/HPC/graphics accelerator background

Role overview

Role family
Hardware Engineering
Level
IC5 — other
Experience
15–30 years
Type
Hybrid (IC + Management)
Remote policy
Hybrid
Visa sponsorship
Not offered

Tech stack analysis

TOOLS
JEDEC standards toolsSI/PI simulation tools (inferred)Timing/jitter analysis tools (inferred)

Green flags

6 items
Salary range explicitly disclosed ($272K–$431.25K), which is transparent and well above market for the rolecompensation

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Benefits breakdown

HEALTH & WELLNESS
Comprehensive benefits package (specific plans not itemized)

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Hiring insights

JD quality
9/10
Urgency
medium
Autonomy
high
Team size
medium (5-15)

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Red flags

PRO3 items
15+ years of DRAM experience with 5+ years on HBM specifically is an extremely narrow talent pool — role may be difficult to staff or expectations may be aspirationalrequirements

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Interview insights

PRO
Rounds
5
Duration
6 wks
Difficulty
very hard
Take-home
No

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Career path

PRO
Next roles
Distinguished Engineer – MemoryFellow – GPU ArchitectureVP of Memory Architecture

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About the company

NVIDIA is the world's leading designer of GPUs and AI computing platforms. Its chips power everything from gaming and data centers to autonomous vehicles and scientific research. With a market cap exceeding $2 trillion, NVIDIA's CUDA platform and AI accelerators have become the backbone of the global AI revolution.

HQSanta Clara, CA, USA
Interview difficultyvery hard
Build vs Maintainbuild
Cross-functionalYes